IBM to offer access to a dual-processor quantum system in 2027

The reason for this split is that IBM plans to use an error-correction “code” that requires a specific number of hardware qubits connected in a specific geometry, along with additional hardware qubits needed to perform operations on that code. You could potentially run some algorithms directly on this hardware without error correction, but it wouldn’t necessarily be optimal. So IBM is also offering a more general-purpose processor in parallel, called Nighthawk.

For past generations of its processors, the company has often developed revisions that improve performance in various ways. So while the roadmap lists only one processor labeled Heron, there were two subsequent revisions to Heron after its release. Throughout 2028, however, the company’s public-facing track will see nothing but revisions to the current generation of processors, called Nighthawk, which started with 120 hardware qubits and the expectation of performing about 5,000 gate operations before errors become too likely to rely on its output.

The previous roadmap called for each generation to boost that number, with 2027’s version expected to hit 10,000 gate operations while keeping the 120 hardware qubit count. But rather than boosting the number of qubits in the processor, it would raise qubit counts by chaining multiple chips together. That’s something that it will eventually have to do to offer a useful number of error-corrected qubits as well. In fact, the company’s most recent roadmap called for linking three Nighthawk processors together in 2026 to create a 360-qubit machine.

It doesn’t look like that’s happening this year. Instead, this year’s Nighthawk r2, released in September, is being offered as a single chip. But IBM is saying it provides a big performance boost compared to r1.

The main reason for the boost is that IBM has dedicated a lot of hardware to resetting qubits to the ground state. This includes physical qubits that aren’t used for computation—the company says there are 458 physical qubits, but only 120 are programmable.

“This is an extra physical qubit that we include on the chip for each programmable qubit that lets us quickly remove the energy from one of our programmable qubits, returning it to the ground state,” Oliver Dial, a VP of Quantum Systems, said. “That capability lets our users run circuits on this chip faster than was ever before possible.”

This isn’t necessary for every operation, but it apparently speeds things up considerably—IBM is reporting up to a 19-fold acceleration of some operations.

(The devices at issue here are physically identical to the programmable qubits but cannot be used as qubits, so the terminology is a bit odd; in some cases, IBM refers to them as “dissipative reset gadgets.”)

Connections

The plan for Nighthawk r3 in 2027 is apparently to retain that performance-enhancing technology and combine it with other hardware improvements to further boost the number of operations that can be performed without errors becoming too likely. It will also significantly increase the qubit count, with a target of 520 programmable qubits. Assuming the ratio of programmable qubits to reset devices remains the same as in the r2, that would suggest the company will be making a chip with roughly 2,000 individual qubit-like devices. That’s about double the size of the largest quantum processor the company has offered to date.

The larger size will keep IBM on its roadmap—sort of. Its existing roadmap promised users access to a single system with 1080 qubits. But it was supposed to get there by linking nine 120-qubit Nighthawk chips. Now, the company plans to offer a 1040-qubit machine (which is close to 1080) but will do so by linking just two chips.

This would seem to suggest that IBM may be having some difficulty getting chip-to-chip communications sorted out. But if so, its executives gave no indication of that. Dial said that IBM has had success “showing four L-couplers joining two Nighthawk R1 processors in the same refrigerator, reaching state transfer fidelities of up to 99.4 percent, very close to our long-term target of 99.9 percent.”

Jerry Chow, IBM’s CTO of Quantum-Centric Supercomputing, said that the speed of these connections is comparable to the qubit interconnections on the chip itself.

Dial acknowledged that the company is still sorting out how many of the couplers would be needed to effectively link chips hosting error-corrected qubits, but that should not impact the current user-facing portion of the roadmap. And the company has already demonstrated a modular dilution refrigerator that will allow it to bring multiple chips and their connectors down to near-absolute-zero temperatures.

IBM’s long-term plan is to use roughly 300 hardware qubits to host a block of 12 logical, error-corrected qubits. At best, that likely means one or possibly two blocks will be hosted on a single chip. To get to 100+ logical qubits, the point where some interesting and useful algorithms can be run, would require IBM to do two things: boost the size of the chip relative to Nighthawk r2 and connect five or more of these chips together. With the changes to its roadmap, it will need to do both by the end of next year to stay on track.